1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for forming a storage node contact opening for a dynamic random access memory (DRAM).
2. Description of the Related Art
In FIG. 1, a semiconductor substrate 10 is shown. A plurality of parallel gate electrode lines 20 with predetermined spacing, and a plurality of parallel bit lines 18 perpendicular to the gate electrode lines 20 and with predetermined spacing are arranged on the semiconductor substrate 10. Between each of the gate electrode lines 20 are conductive plugs (or landing pads) 12 for storage nodes (or conductive pads) 16 and conductive plugs 14 for a bit lines 18. Each of the storage nodes 16 is electrically connected through a buried contact (referred to below as a “BC”) to a conductive plug 12. Each of the bit lines 18 is electrically connected through a direct contact (referred to below as a “DC”) to a conductive plug 14. A memory cell formed on semiconductor substrate 10 comprises a storage node 16, a conductive plug 14 for a bit line 18, and an electrode line 20 interposed therebetween.
Referring to FIGS. 2A–2C, on the semiconductor substrate 10 are formed a conductive plug 14 (referred to below as a “DC plug”) that electrically connects a bit line 18 (referred to below as a “BL”) to the semiconductor substrate 10, and a conductive plug 12 (referred to below as a “BC plug”) that electrically connects a storage node 16 to the semiconductor substrate 10. After formation of a bit line 18, a contact opening (or contact hole) for forming a storage node 16 is formed. Then the storage node 16 is formed on the BC plug 12, as shown in FIG. 2A. The process steps required to form these features are well known to those skilled in the art.
As the integration level of a semiconductor device (in particular, a DRAM) formed on the semiconductor substrate 10 increases, the depth of the contact opening (for forming a storage node 16 to connect to a BC plug 12) increases and the diameter at the bottom of the contact opening decreases. The height of the contact opening increases in proportion to the decrease in the wiring width of bit line 18. It takes additional etching time to form a deeper contact opening to connect a storage node 16 to a BC plug 12. As a result, the contact opening is overetched so that the upper diameter of the contact opening increases.
If the increased diameter contact opening (i.e., the BC opening) is misaligned, the storage node 16 in the contact opening may be etched in a portion 22 during an etching process for forming the storage node 16. Thus, if a dielectric film (not shown) and a plate electrode (not shown) are formed on an overall surface of the semiconductor substrate 10, it may be impossible to insulate a storage node 16 from the plate electrode because the dielectric characteristics of the dielectric film may be degraded in the portion 22 that is misaligned as a result of overetching. In the worst case, the storage node 16 may fall down due to overetching. Furthermore, the deeper the contact opening is, the more difficult it is to clean an internal portion of the contact opening.
Following is a description of a technique which has been suggested to solve the foregoing problems. Referring to FIGS. 3A–3C, a DC opening is simultaneously formed on a BC formation region (conductive plug 12′ for a storage node) with a DC opening. The DC opening connects a bit line 18′ to a conductive plug 14′. After formation of bit line material on the overall surface of a semiconductor substrate 10, a bit line 18′ is formed using a conventional photo-etching process. At the same time, a plug 24 is also formed at the DC opening on the BC plug 12′ from the same material as the bit line 18′ by controlling the etching time of the bit line material, as shown in FIG. 3A.
Forming the plug 24 on the BC plug 12′ reduces the depth of the BC opening. As shown in FIG. 3A, the depth of the BC opening is reduced as much as the thickness D1 of an insulating layer 26. It is, however, still difficult to overcome the thickness D2 of the bit line 18′ and an interlayer insulating film 28 when the BC opening is formed. The prior problems may also occur when the BC contact opening and the storage node 16′ are formed.